1. Field of Invention
The present invention relates to a semiconductor package structure and the applications thereof, and more particularly relates to a chip stacked package structure and the method for manufacturing the same.
2. Description of Related Art
Nowadays, electronic devices are developed to provide increased functionality. Single chips with multiple integrated functions are therefore required to ensure and the chips can fit into electronic devices of limited. To integrate more functions in a single package, the package structure of the chip has evolved from a two-dimensions to three-dimensions and from a single-die package structure to a multiple-die package structure.
A system-in-package is a chip-stacked package structure with several chips with multiple functions integrated into a package structure, wherein these chips are stacked on a substrate by surface mount technology (SMT), so as to improve the packing process and to decrease the chip size. Whereby the system-in-package has the advantage of a small size, high operating frequency, high speed and low cost.
FIG. 5 illustrates a cross sectional view of a conventional chip stacked structure 500. The chip-stacked package structure 700 includes a substrate 510, a first chip 520, a second chip 530 and a plurality of bonding wires, such as bonding wires 540 and 550. The first chip 520 disposed on the substrate 510 is electrically connected to the substrate 510 by the bonding wire 540, and the second chip 530 stacked on the first chip 520 is electrically connected to the substrate 510 by the bonding wire 550.
To accommodate the arrangement of the bonding wire (the bonding wire 540) connected on the lower chip (the first chip 520); the size of the upper chip (the second chip 530 stacked on the first chip 520) must be smaller than that of the lower chip in the conventional design. Thus the design flexibility and the number of chips stacked in a single package are limited. Furthermore, it is necessary to extend the bonding wires in connecting the chips of small size with the substrate, whereby the radian of the bonding wires may be increased. Consequently, when a subsequent stamping process is conducted, the bonding wires may be wrenched off so as to make the electrical connection short and to decrease its manufacture yield.
To resolve the aforementioned problems, an alternative conventional chip stacked structure is provided. FIG. 6 illustrates a cross view cross-section view of an alternative conventional chip stacked structure 800. The chip-stacked package structure 600 includes a substrate 610, a first chip 620, a second chip 630, a plurality of bonding wires, such as bonding wires 640 and 650, and a dummy chip 660 disposed between the first chip 620 and the second chip 630. The first chip 620 disposed on the substrate 610 has a bonding pad 670 electrically connected to the substrate 610 by the bonding wire 640, and the dummy chip 660 is stacked on the first chip 620. The second chip 630 stacked on the dummy chip 660 has a bonding pad 680 electrically connected to the substrate 610 by the bonding wire 650. Since the size of the dummy chip is smaller than the size of the first chip 620 and the second chip 630, there provides enough wiring space between the lower chip (the first chip 620) and the upper chip (the second chip 630) for the bonding wire 640 to electrically bond on the lower chip. Accordingly, in this case the size of the upper chip (the second chip 630) is no longer limited.
However, using the dummy can increase the thickness of the pancake structure and may conflict with the trend of package size minimization. Therefore, it is desirable to provide an advanced chip-stacked package structure designed to improve the process yield so as to lower the manufacturing costs.